A scalable and efficient convolutional neural network accelerator using HLS for a system-on-chip design

نویسندگان

چکیده

This paper presents a configurable convolutional neural network accelerator (CNNA) for system-on-chip (SoC). The goal was to accelerate inference in different deep learning networks on an embedded SoC platform. presented CNNA has scalable architecture that uses high-level synthesis (HLS) and SystemC the hardware . It can any (CNN) exported from Keras Python supports combination of convolutional, max-pooling, fully connected layers. A training method with fixed-point quantised weights is proposed paper. template-based, enabling it scale targets Xilinx Zynq approach enables design space exploration , which makes possible explore several configurations during C RTL simulation, fitting desired platform model. CNN VGG16 used test solution Ultra96 board using productivity (PYNQ). result gave high level accuracy autoscaled Q2.14 format compared similar floating-point able perform 2.0 s while having average power consumption 2.63 W, corresponds efficiency 6.0 GOPS/W. • single computation engine FPGA acceleration. template based HLS synthesise exploration. acceleration controlled host CPU PYNQ framework Python. Dynamic autoscaling weights. implementation state-of-the-art.

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ژورنال

عنوان ژورنال: Microprocessors and Microsystems

سال: 2021

ISSN: ['0141-9331', '1872-9436']

DOI: https://doi.org/10.1016/j.micpro.2021.104363